In a synchronous digital system, a master or system clock is distributed to all elements performing synchronous functions. In order to co-ordinate the switching and logical processes, it is essential that each element be connected to a clock signal line wherein the variation in clock pulse leading edge is, within a tight tolerance, simultaneous with the occurrence of the leading edge of the other clock pulses distributed to the other elements. The difference in time between the leading edge of one clock pulse on one clock line, and the leading edge of a corresponding clock pulse on another clock line, where both are derived from the same master or system clock, is called the clock skew and it is measured in fractions of a second.
Since it is impractical to have a single master clock drive every function in a synchronous digital system, a group of local clock lines are derived from the master clock input by multiple integrated circuit power and isolation amplifiers called buffers. It is the differences in the response time, called delay time, of these buffer integrated circuits that causes clock skew. Even when the delay time variance input to output between the buffers on a single integrated circuit chip is acceptably low, the guaranteed/specified range of delay times for all integrated circuit buffers typically is too wide to just straightforwardly connect in parallel the inputs of two integrated circuit buffers and expect to always yield outputs with acceptable clock skews. Statistics predict that with randomly selected circuits sometimes two IC chips within the range will be closely enough matched in propagation delay time will be selected, while other times the two IC chips selected randomly will not be closely enough matched in regard to delay times and an unacceptable clock skew between branches of the clock line will result.
The standard techniques of solving this problem are either to put in a delay circuit at the common (i.e., paralleled) input of each buffer chip and then adjust the delay circuit to compensate for the variation in buffer chips, or to select and grade by testing all buffer chips to be used into matched groups that have propagation delays close enough to each other to prevent an unacceptable clock skew from resulting. The former method requires the expense of extra components to form the delay circuits and requires adjustment of the delay circuits by technicians with the aid of expensive test equipment. The latter method requires technicians to operate automated test equipment testing and recording the propagation delay of each buffer into groups with very nearly the same propagation delay for future installation. Further, if either component fails, the adjustment or selection procedure, whichever the case may be, will have to be repeated to repair the circuit.
It is an object of this invention to provide an anti-clock skew distribution system without the cost and repair problems of matched or adjusted components. It is a further object of this invention to provide an anti-clock skew distribution system readily available "off the shelf" components.